Gapped signals are widely used in Optical Transport Network (OTN), broadcast video as well as many other application areas. One of the key requirements of an OTN is to insert plesiochronous payloads into an OTN wrapper. That is, because the data transmission rate and the rate of the payload source may not be exactly the same, they may drift with respect to one another. One approach to solve the issue to is to generate a reference clock with missing clock edges (or gaps) to keep the incoming and outgoing data rates synchronized.
A gapped signal by its nature carries significant amount of jitter, which usually is not tolerated by the downstream consumer circuitry. A jitter attenuating phase locked loop (PLL) is typically used to create an output signal that has the same average frequency as the gapped signal with the jitter component attenuated. When the jitter component is interspersed in the gapped signal at a relatively high frequency, it can be effectively attenuated by the PLL. In addition, jitter with short durations can be removed more easily than those with long periods.
Jitter attenuation issues are compounded with the bandwidth limits of PLLs used in frequency synthesizers, especially for incoming signals carrying stuffed bytes, such as those introduced during justification processes. Asynchronous mapping of Constant Bit Rate (CBR) clients, such as SONET or SDH, typically adapts the bit rates of SONET/SDH to the asynchronous OTUk (k=1, 2, 3) bit rate for transportation using byte stuffing, or justification, mechanism in order to increase bit-rate tolerance. If the client signal rate is lower than an OTUk rate after adjustment due to stuffing/overhead, extra stuff bytes are inserted to fill out the OTUk frame. Similarly, if the client signal rate is higher than OTUk after adjustment due to stuffing/overhead, the stuff bytes can be replaced with client information to increase the OTUk payload capacity.
A justification process adds control (JC) bytes to a data frame to control the negative justification opportunity (NJO) or positive justification opportunity (PJO). Introduction of the JC bytes, along with justification control bits indicating the addition of the JC bytes causes a shift of data transmission rate. During a corresponding demapping process, the JC bytes and JC control bites, or the stuffing information, are interpreted and incorporated while reconstructing the CBR client signal clock. A phase locked loop (PLL) is typically used for the frequency synthesis. Ideally, the data signal is read out under control of a smooth clock.
The extra bytes or gaps introduced by such a justification process can cause large phase steps, or jitter, of low frequency in demapping process. Conventional jitter attenuation methods and systems utilizing a PLL have limited bandwidth for jitter attenuation. For example, a bandwidth of 300 Hz is specified in ITU-T G.8251 for demapping. It has been observed that conventional jitter attenuation PLLs are inefficient in removing jitter caused by the justification processes.